Staff Engineer, ASIC STA

Req. ID: JR103317 Staff Engineer, ASIC STA Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community. # Role: The team member will typically work on processors, controller architectures or ASICs for Enterprise SSD Group. Should be proficient in block level low power aware floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC and tape out activities. Requirements Skills Required * 8-14 years of relevant experience in Synthesis/STA * Good understanding of overall design Flow RTL to GDS. * Hands on Experience on Constraints Generation, timing closure of full chip on Hierarchical Designs * Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools. * Hands on Experience on Equivalent Checks with Synopsys / Cadence Tools. * Good knowledge on Timing Budgets. * Knowledge on Perl / TCL / Python scripting language * Experience on multi voltage designs using CPF/UPF. * Hands on experience on power analysis using PTPX * Good understanding of VHDL / Verilog Constructs. Responsibilities * Responsible for Block/ Chip Tile Synthesis to achieve the best PPA. * Constraint Generation & Timing closure for Block and Full Chip SOC for complex hierarchical Designs for all the Modes. * Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts . * Able to work on low power Intent & verify low power intent with minimal supervision. * Responsible for Logical equivalence checks & Low Power Checks. * Early RTL analysis for Clocking, Power , DFT coverage & suggestions to Designer on the improvements. * Support Verification team to enable GLS. Preferred Skills: ·Strong verbal communication skills ·Cadence PnR tools ·Formal verification experience ·Digital electronics and microprocessors experience Job Profile(s): ASIC Engineer 4 Relocation level: (TBD) Before Getting Started Please review Micron’s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence. * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process. ​​​​ As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.